This invention relates to latch circuits. More specifically, this invention relates to latches that have significantly reduced turn-ON and turn-OFF times.
FIG. 1 shows a conventional latch 100 formed by a cross-coupled pair of transistors, transistors 120 and 130. Hereafter, the term cross-coupled transistors is used herein to refer to two transistors wherein the base of one is connected to the collector-emitter circuit of the other. Two additional transistors, transistors 110 and 140, are coupled to the SET 190 and RESET 195 inputs of the circuit, and are labeled SET and RESET because they are used to trigger changes in the output state of latch 100. Transistors 110, 120, 130 and 140 may each include a shottky diode, such as shottky diode 145, across their respective collector/base junctions to prevent saturation, but only shottky diode 145 is shown to simplify the drawing.
The following is an exemplary truth table for the operation of the latch in FIG. 1:
RESETSETQn+1A00QnB011C100D11not usedThe outputs are labeled Q 170 and {overscore (Q)} 180. These outputs are complementary—i.e., when Q 170 is high, {overscore (Q)} 180 is low and vice versa.
Latch 100 is considered SET when Q 170 is high and {overscore (Q)} 180 is low. It is RESET when Q 170 is low and {overscore (Q)} 180 is high. The operation of transistors 110, 120, 130 and 140 to produce the results found in the truth table above is well known.
One potential problem exists, however, with this circuit, as follows.
In normal storage operation, i.e., the state where both inputs SET 190 and RESET 195 are held close to ground, the outputs, Q 170 and {overscore (Q)} 180, retain their previous state. This operation is shown in state A in the table above. In this state, the base of the SET and RESET transistors, transistors 110 and 140 respectively, are also held close to ground by SET 190 and RESET 195 inputs. To change the latch state, the base of one of transistors 110 and 140 must be pulled up by at least a Vbe (approximately 700 millivolts) in order to turn the transistor ON and are, therefore, voltage-driven—i.e., require a significant change in voltage to turn ON. This substantial difference in voltage required to alter the output value of the latch causes a delay because of the time constant associated with charging the base capacitance of the SET or RESET transistors with the full Vbe voltage and charging the base capacitance of the device driving the base of the SET or RESET transistors with the full Vbe voltage. The delay slows the operation of the latch. This problem is particularly relevant when the drive to the SET or RESET transistors is from the collector of a PNP.
There are several ECL (emitter-coupled logic) type latches that are commonly used to overcome this problem. They provide a solution by operating all the transistors in the active region and not in the saturated region. This reduces turn-OFF and turn-ON times because the transistors are not being fully charged and fully drained for each state change of the latch. However, these latches tend to be more complex than common latches and require input/output level shifting.
Therefore, it would be desirable to provide a simple latch that changes state in a substantially reduced time period.